Low voltage complementary metal oxide semiconductor process tri-state buffer
US7432739B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2006 |
| Grant date | Oct 7, 2008 |
| Priority date | — |
| Expiry date | Oct 27, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09429
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low voltage complementary metal oxide semiconductor (CMOS) process tri-state buffer includes a logic device, a biasing device and a switch device. The logic device receives an input signal and an enable signal and generates a first control signal and a second control signal. The biasing device receives the first control signal and thus controls a voltage level of a third control signal. The switch device receives the second and third control signals and respectively couples an output terminal to a first external voltage source and a second external voltage source when the second and third control signals are enabled. When the enable signal is disabled, the second and third control signals are simultaneously disabled so that the output terminal is floating with respect to the first and second external voltage sources and the output terminal is held in a high impedance state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.