System and method for forcing an SRAM into a known state during power-up
US7433224B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2000 |
| Grant date | Oct 7, 2008 |
| Priority date | — |
| Expiry date | Feb 7, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is disclosed a static random access memory (SRAM) device that stores an embedded program that is accessible when the SRAM device is powered up. The SRAM device comprises a plurality of storage cells, each of the storage cells comprises a data latch having an input and an output, wherein the data latch comprises a) a first inverter having an input coupled to the first I/O line and an output coupled to the second I/O line, and b) a second inverter having an input coupled to the second I/O line and an output coupled to the first I/O line. The storage cell also comprises a biasing circuit that forces at least one of the first and second I/O lines to a known logic state when power is applied to the SRAM device. The known logic state comprises one bit in the embedded program.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.