Translation lookaside buffer prediction mechanism
US7434027B2 · kind B2 · utility
3Cited by
1References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2006 |
| Grant date | Oct 7, 2008 |
| Priority date | — |
| Expiry date | Sep 27, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/654
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment a central processing unit (CPU) is disclosed. The CPU includes a translation lookaside buffer (TLB). The TLB predicts a set index value prior to the generation of an effective address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.