Placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline
US7434033B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2006 |
| Grant date | Oct 7, 2008 |
| Priority date | — |
| Expiry date | Jul 26, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/524
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Mechanisms for placing a processor into a gradual slow down mode of operation are provided. The gradual slow down mode of operation comprises a plurality of stages of slow down operation of an issue unit in a processor in which the issuance of instructions is slowed in accordance with a staging scheme. The gradual slow down of the processor allows the processor to break out of livelock conditions. Moreover, since the slow down is gradual, the processor may flexibly avoid various degrees of livelock conditions. The mechanisms of the illustrative embodiments impact the overall processor performance based on the severity of the livelock condition by taking a small performance impact on less severe livelock conditions and only increasing the processor performance impact when the livelock condition is more severe.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.