Track buffer in a parallel decoder
US7434148B2 · kind B2 · utility
1Cited by
5References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2004 |
| Grant date | Oct 7, 2008 |
| Priority date | — |
| Expiry date | Jul 31, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/4107
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method (700) and apparatus (600) are described for performing 2M−1 parallel ACS operations to generate 2M path metric outputs and buffering the 2M path metric outputs in connection with a track buffer (112) in an Ultrawide Bandwidth (UWB) receiver for decoding a message sequence encoded according to a convolutional code. Contents of the track buffer are updated in accordance with Register Exchange and outputs from the track buffer can further be input to a voting unit (114) where a voting scheme can be applied and a decision rendered as to the originally transmitted message sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.