Method and apparatus for parallel data preparation and processing of integrated circuit graphical design data
US7434185B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2006 |
| Grant date | Oct 7, 2008 |
| Priority date | — |
| Expiry date | Nov 28, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for implementing an ORC process to facilitate physical verification of an integrated circuit (IC) graphical design. The method includes partitioning the IC graphical design data into files by a host machine such that the files correspond to regions of interest or partitions with defined margins, dispersing the partitioned data files to available cpus within the network, processing of each job by the cpu receiving the file, wherein artifacts arising from bisection of partitioning margins during the partitioning, including cut-induced false errors, are detected and removed, and the shape-altering effects of such artifact errors are minimized and transmitting the results of processing at each cpu to the host machine for aggregate processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.