Techniques for optimizing design of a hard intellectual property block for data transmission

US7434192B2 · kind B2 · utility

Assignee

• Altera Corporation · US

Inventors

• Darren van Wageningen · Gatineau, CA
• Curt Wortman · San Jose, US
• Boon Jin Ang · Butterworth, MY
• Thow Pang Chong · Bayan Lepas, MY
• Dan Mansur · Chippewa Falls, US
• Ali Burney · Fremont, US

Key dates

• Filing date: Dec 13, 2004
• Grant date: Oct 7, 2008
• Expiry date: Feb 27, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H04L25/14
• WIPO field: Digital communication
• WIPO sector: Electrical engineering

Abstract

Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be run using a reduced number of parallel data paths, which consumes substantially less logic resources. Also, the HIP block channel alignment logic circuits can be processed at the higher HIP core clock rate in serial, decreasing lock latency time. Techniques are provided for implementing error handling for transmitted data in programmable logic circuits. The programmable logic circuits can be configured to implement error generation and error monitoring functions that are tailored for any application. Alternatively, the logic elements can be configured to perform other functions for applications that do not require error handling. The phase skew between data and clock signals on an integrated circuit are reduced by routing clock signals along with the data signals to each circuit block.