Alloyed underlayer for microelectronic interconnects
US7435679B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2004 |
| Grant date | Oct 14, 2008 |
| Priority date | — |
| Expiry date | Nov 18, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/694
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Apparatus and methods of fabricating a microelectronic interconnect having an underlayer which acts as both a barrier layer and a seed layer. The underlayer is formed by co-depositing a noble metal and a barrier material, such as a refractory metal, or formed during thermal post-treatment, such as thermal annealing, conducted after two separately depositing the noble metal and the barrier material, which are substantially soluble in one another. The use of a barrier material within the underlayer prevents the electromigration of the interconnect conductive material and the use of noble material within the underlayer allows for the direct plating of the interconnect conductive material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.