Semiconductor device comprising a superlattice channel vertically stepped above source and drain regions
US7436026B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 14, 2004 |
| Grant date | Oct 14, 2008 |
| Priority date | — |
| Expiry date | Jan 31, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A semiconductor device may include a semiconductor substrate and at least one metal oxide semiconductor field-effect transistor (MOSFET). The at least one MOSFET may include spaced apart source and drain regions in the semiconductor substrate, and a superlattice channel including a plurality of stacked groups of layers on the semiconductor substrate between the source and drain regions. The superlattice channel may have upper surface portions vertically stepped above adjacent upper surface portions of the source and drain regions. Each group of layers of the superlattice channel may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor. The at least one MOSFET may additionally include a gate overlying the superlattice channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.