Patent assignee · US · COMPANY

MEARS TECHNOLOGIES, INC.

29Patents
22Active
29Granted
53Portfolio score

Filing activity: Sep 3, 2004 → Nov 21, 2014 · 20 expiring within 5 years

Most-cited patents

PatentTitleAreaCited byStatus
US7781827B2 Semiconductor device with a vertical MOSFET including a superlattice and related methods Electricity 131 Active
US7514328B2 Method for making a semiconductor device including shallow trench isolation (STI) regions with a superlattice therebetween Electricity 120 Active
US7517702B2 Method for making an electronic device including a poled superlattice having a net electrical dipole moment Electricity 117 Active
US7446002B2 Method for making a semiconductor device comprising a superlattice dielectric interface layer Electricity 115 Expired
US7531828B2 Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions Electricity 112 Active
US7612366B2 Semiconductor device including a strained superlattice layer above a stress layer Electricity 112 Active
US7531829B2 Semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance Electricity 111 Active
US7598515B2 Semiconductor device including a strained superlattice and overlying stress layer and related methods Electricity 111 Active
US7625767B2 Methods of making spintronic devices with constrained spintronic dopant Electricity 110 Active
US7880161B2 Multiple-wavelength opto-electronic device including a superlattice Emerging Cross-Sectional Technologies 109 Active
US7436026B2 Semiconductor device comprising a superlattice channel vertically stepped above source and drain regions Electricity 109 Expired
US7700447B2 Method for making a semiconductor device comprising a lattice matching layer Electricity 109 Active
US7928425B2 Semiconductor device including a metal-to-semiconductor superlattice interface layer and related methods Electricity 108 Active
US7659539B2 Semiconductor device including a floating gate memory cell with a superlattice channel Electricity 108 Active
US7303948B2 Semiconductor device including MOSFET having band-engineered superlattice Electricity 107 Expired
US7432524B2 Integrated circuit comprising an active optical device having an energy band engineered superlattice Electricity 107 Expired
US7586116B2 Semiconductor device having a semiconductor-on-insulator configuration and a superlattice Electricity 107 Active
US7446334B2 Electronic device comprising active optical devices with an energy band engineered superlattice Electricity 107 Expired
US7435988B2 Semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channel Electricity 107 Expired
US7491587B2 Method for making a semiconductor device having a semiconductor-on-insulator (SOI) configuration and including a superlattice on a thin semiconductor layer Electricity 107 Active
US7531850B2 Semiconductor device including a memory cell with a negative differential resistance (NDR) device Electricity 106 Active
US7863066B2 Method for making a multiple-wavelength opto-electronic device including a superlattice Emerging Cross-Sectional Technologies 106 Active
US8389974B2 Multiple-wavelength opto-electronic device including a superlattice Emerging Cross-Sectional Technologies 106 Active
US7718996B2 Semiconductor device comprising a lattice matching layer Electricity 106 Active
US7812339B2 Method for making a semiconductor device including shallow trench isolation (STI) regions with maskless superlattice deposition following STI formation and related structures Electricity 106 Active

Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.