Wafer having scribe lanes suitable for sawing process, reticle used in manufacturing the same, and method of manufacturing the same
US7436047B2 · kind B2 · utility
2Cited by
3References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 11, 2006 |
| Grant date | Oct 14, 2008 |
| Priority date | — |
| Expiry date | Nov 14, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer that is less susceptible to chipping or peeling during a sawing process is disclosed. The wafer includes a plurality of chips, scribe lanes formed between the plurality of chips, and a passivation film, which is formed on the plurality of chips and the scribe lanes and has a plurality of perforations, e.g. slit patterns engraved on each scribe lane. A photolithography reticle and method of manufacturing the wafer are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.