Packaging method of a plurality of chips stacked on each other and package structure thereof
US7436055B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 25, 2006 |
| Grant date | Oct 14, 2008 |
| Priority date | — |
| Expiry date | Sep 13, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A package structure with a plurality of chips stacked on each other includes a substrate, a first chip and second chip. The substrate has a dielectric layer, a metal layer having a conducting trace area and a shielding area formed on the dielectric layer, and a solder mask formed on the conducting trace area. The first chip and the second chip are electrically connected to the conducting trace area and arranged on the solder mask respectively. The first chip has a package body connected with one surface of the metal layer for arranging the first chip between the solder mask and the shielding area of the metal layer. The second chip has a package body connected with the other surface of the metal layer for arranging the second chip between the solder mask and the shielding area of the metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.