Configurable high-speed memory interface subsystem
US7437500B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 5, 2005 |
| Grant date | Oct 14, 2008 |
| Priority date | — |
| Expiry date | Jun 6, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A core including a write logic IP block, a read logic IP block, a master delay IP block and an address and control IP block. The write logic IP block may be configured to communicate data from a memory controller to a double data rate (DDR) synchronous dynamic random access memory (SDRAM). The read logic IP block may be configured to communicate data from the double data rate (DDR) synchronous dynamic random access memory (SDRAM) to the memory controller. The master delay IP block may be configured to generate one or more delays for the read logic IP block. The address and control logic IP block may be configured to control the write logic IP block and the read logic IP block. The core is generally configured to couple the double data rate (DDR) synchronous dynamic random access memory (SDRAM) and the memory controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.