Terence J. Magee
17Patents
5h-index
24Co-inventors
62Inventor score
Filing activity: Aug 5, 2005 → Jun 16, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7437500B2 | Configurable high-speed memory interface subsystem | Physics | 25 | Active |
| US7454303B2 | System and method for compensating for PVT variation effects on the delay line of a clock signal | Physics | 12 | Active |
| US8453096B2 | Non-linear common coarse delay system and method for delaying data strobe | Physics | 8 | Active |
| US10009197B1 | Method and apparatus for intersymbol interference compensation | Physics | 7 | Active |
| US9324409B1 | Method and apparatus for gating a strobe signal from a memory and subsequent tracking of the strobe signal over time | Physics | 6 | Active |
| US7969799B2 | Multiple memory standard physical layer macro function | Physics | 4 | Active |
| US9330749B1 | Dynamic selection of output delay in a memory control device | Emerging Cross-Sectional Technologies | 4 | Active |
| US10103718B1 | Recalibration of source synchronous systems | Electricity | 3 | Active |
| US7865661B2 | Configurable high-speed memory interface subsystem | Physics | 3 | Active |
| US9331701B1 | Receivers and methods of enabling the calibration of circuits receiving input data | Electricity | 3 | Active |
| US9281049B1 | Read clock forwarding for multiple source-synchronous memory interfaces | Physics | 3 | Active |
| US7605628B2 | System for glitch-free delay updates of a standard cell-based programmable delay | Electricity | 3 | Active |
| US8743634B2 | Generic low power strobe based system and method for interfacing memory controller and source synchronous memory | Physics | 2 | Active |
| US9355696B1 | Calibration in a control device receiving from a source synchronous interface | Physics | 2 | Active |
| US9557766B1 | High-speed serial data interface for a physical layer interface | Electricity | 2 | Active |
| US9224444B1 | Method and apparatus for VT invariant SDRAM write leveling and fast rank switching | Emerging Cross-Sectional Technologies | 0 | Active |
| US11789641B2 | Three dimensional circuit systems and methods having memory hierarchies | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.