Write-back cache with different ECC codings for clean and dirty lines with refetching of uncorrectable clean lines
US7437597B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 2005 |
| Grant date | Oct 14, 2008 |
| Priority date | — |
| Expiry date | Jan 30, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1064
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A write-back cache has error-correction code (ECC) fields storing ECC bits for cache lines. Clean cache lines are re-fetched from memory when an ECC error is detected. Dirty cache lines are corrected using the ECC bits or signal an uncorrectable error. The type of ECC code stored is different for clean and dirty lines. Clean lines use an error-detection code that can detect longer multi-bit errors than the error correction code used by dirty lines. Dirty lines use a correction code that can correct a bit error in the dirty line, while the detection code for clean lines may not be able to correct any errors. Dirty lines' ECC is optimized for correction while clean lines' ECC is optimized for detection. A single-error-correction, double-error-detection (SECDED) code may be used for dirty lines while a triple-error-detection code is used for clean lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.