Patent · US Active

Method and device for determining the time response of a digital circuit

US7437696B2 · kind B2 · utility

2Cited by
10References
23Claims
0Family size

Assignee

Inventors

Key dates

Filing dateSep 29, 2005
Grant dateOct 14, 2008
Priority date
Expiry dateAug 9, 2026

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG01R31/31725
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

A method and a device determine a time response of a digital circuit. The time response is determined as a time difference between a data delay of a data path of the digital circuit, and a clock delay of a clock signal, which causes storage of a data item on the data path, taking into account a check. The check is determined dependent on a data slew of a signal on the data path and a clock slew of the clock signal in such a way that a positive time difference ensures the correct saving of the data item.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.