Technique for compensating for substrate shrinkage during manufacture of an electronic assembly
US7439083B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2005 |
| Grant date | Oct 21, 2008 |
| Priority date | — |
| Expiry date | Dec 20, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/1126
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Substrate shrinkage that occurs during manufacture of an electronic assembly is compensated for by the incorporation of a horizontal line, having a plurality of vertical graduations, across a horizontal portion of a substrate and a vertical line, having a plurality of horizontal graduations, across a vertical portion of the substrate. The substrate is then cured and an amount of substrate shrinkage is determined, based upon a location change in the graduations of the horizontal and vertical lines. In this manner, solder can be properly provided on solder pads of the substrate responsive to the amount of substrate shrinkage. As such, electronic components can be properly mounted to the solder pads of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.