Thermally stable BiCMOS fabrication method and bipolar junction transistors formed according to the method
US7439119B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2006 |
| Grant date | Oct 21, 2008 |
| Priority date | — |
| Expiry date | Nov 12, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/401
Abstract
A method for forming BiCMOS integrated circuits and structures formed according to the method. After forming doped wells and gate stacks for the CMOS devices and collector and base regions for the bipolar junction transistor, an emitter layer is formed within an emitter window. A dielectric material layer is formed over the emitter layer and remains in place during etching of the emitter layer and removal of the etch mask. The dielectric material layer further remains in place during source/drain implant doping and activation of the implanted source/drain dopants. The dielectric material layer functions as a thermal barrier, to limit out-diffusion of the emitter dopants during the activation step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.