Memory structure and method of manufacturing a memory array
US7439133B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 2, 2006 |
| Grant date | Oct 21, 2008 |
| Priority date | — |
| Expiry date | Apr 27, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0458
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory structure formed between two doping regions in a semiconductor substrate includes two conductive blocks functioning as floating gates formed at two sides of a first conductive line functioning as a select gat and insulated from the first conductive line with two first dielectric spacers therebetween, wherein the two conductive blocks each have a raised top and raised parts of sides relative to the top of the first conductive line. A first dielectric layer is formed on the tops and the parts of the sides of the two conductive blocks. A second conductive line functioning as a word line is formed on the first dielectric layer, wherein the second conductive line has a part deposited between the two conductive blocks and is substantially perpendicular to the first conductive line and two doping region functioning as bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.