Hybrid orientation CMOS with partial insulation process
US7439542B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 5, 2004 |
| Grant date | Oct 21, 2008 |
| Priority date | — |
| Expiry date | Jun 16, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D87/00
Abstract
The present invention provides a method of integrated semiconductor devices such that different types of devices are formed upon a specific crystallographic orientation of a hybrid substrate. In accordance with the present invention, junction capacitance of one of the devices is improved in the present invention by forming the source/drain diffusion regions of the device in an epitiaxial semiconductor material such that they are situated on a buried insulating layer that extends partially underneath the body of the second semiconductor device. The second semiconductor device, together with the first semiconductor device, is both located atop the buried insulating layer. Unlike the first semiconductor device in which the body thereof is floating, the second semiconductor device is not floating. Rather, it is in contact with an underlying first semiconducting layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.