Method for fabricating metal gate structures
US7439571B2 · kind B2 · utility
2Cited by
11References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 2, 2005 |
| Grant date | Oct 21, 2008 |
| Priority date | — |
| Expiry date | May 2, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising source/drain and gate regions, wherein the gate region comprises a metal layer disposed on a gate dielectric layer, and then laser annealing the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.