Tri-gate integration with embedded floating body memory cell using a high-K dual metal gate

US7439588B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Ibrahim Ban · Beaverton, US
• Peter L. D. Chang · Portland, US

Key dates

• Filing date: Dec 13, 2005
• Grant date: Oct 21, 2008
• Expiry date: Aug 2, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/62

Abstract

Dual-gate memory cells and tri-gate CMOS devices are integrated on a common substrate. A plurality of silicon bodies are formed from a monocrystalline silicon on the substrate to define a plurality of transistors including dual-gate memory cells, PMOS transistors, and NMOS transistors. An insulative layer is formed overlying the silicon body of the memory cell. A layer of a high-k dielectric and at least a metal layer cover the silicon bodies and their overlying layers. Next, gain regions of the transistors are filled with polysilicon. Thus, a gate is formed on the top surface and both sidewalls of a tri-gate transistor. Thereafter, the high-k dielectric and the metal layer overlying the insulative layer of the memory cell are removed to expose the insulative layer. Thus, two electrically-isolated gates of the memory cell are formed.