Semiconductor memory device
US7440303B2 · kind B2 · utility
4Cited by
4References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 14, 2007 |
| Grant date | Oct 21, 2008 |
| Priority date | — |
| Expiry date | Mar 14, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes resistance memory elements that are coupled to selection transistors addressed by word lines and bit lines. The memory elements are read by read/write lines arranged parallel to the word lines. Two successive memory elements along a read/write line are coupled to selection transistors that are coupled to different word lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.