Memory write timing system
US7440312B2 · kind B2 · utility
4Cited by
5References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2006 |
| Grant date | Oct 21, 2008 |
| Priority date | — |
| Expiry date | Oct 3, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/41
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory write timing system includes a modified memory bitcell including a storage device and a write/read circuit for writing/reading data to/from the storage device; and an output circuit for detecting the current state of the storage device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.