Floating body control in SOI DRAM
US7440353B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2006 |
| Grant date | Oct 21, 2008 |
| Priority date | — |
| Expiry date | Sep 21, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method wherein a DRAM memory device on an integrated circuit (IC) uses a control logic device to initiate a body refresh operation for maintaining a low voltage at a floating body and discourage data loss. A plurality of DRAM cells are connected to a first word line circuit and a first bit line circuit. The control logic device is coupled to the DRAM memory device and the IC for initiating the body refresh cycle. The control logic communicates with a first bit line and word line circuits and communicates with a reference word line and bit line circuits. A sense amplifier circuit and signal is provided for amplifying the voltage at the first bit line and the reference bit line (or bit line bar circuit). The body refresh cycle includes deactivating the first word line voltage while the first bit line and reference bit line voltages continue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.