Method and apparatus for synchronizing clocks on packet-switched networks
US7440474B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2004 |
| Grant date | Oct 21, 2008 |
| Priority date | — |
| Expiry date | Mar 26, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0664
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
The present invention is directed to the synchronization of clock frequencies across packet data networks. In particular, one or more communication endpoints may produce a clock signal that is synchronized to a master clock source. Synchronization is performed by providing timing packets containing information regarding a number of clock cycles counted on the master clock source to a controlled clock source. The controlled clock source uses the provided count to increment a counter value. At the same time, the counter value on the controlled clock source is decremented by the controlled clock source clock. The resulting counter value is used to address a correction table. A correction value from the correction table is applied to the frequency control input of the controlled clock source clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.