Cyclic flash memory wear leveling
US7441067B2 · kind B2 · utility
279Cited by
42References
1Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 15, 2004 |
| Grant date | Oct 21, 2008 |
| Priority date | — |
| Expiry date | Apr 10, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A re-programmable non-volatile memory system, such as a flash EEPROM system, having its memory cells grouped into blocks of cells that are simultaneously erasable is operated in a manner to level out the wear of the individual blocks through repetitive erasing and re-programming. This may be accomplished without use of counts of the number of times the individual blocks experience erase and re-programming but such counts can optionally aid in carrying out the wear leveling process. Individual active physical blocks are chosen to be exchanged with those of an erased block pool in a predefined order.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.