Systems and methods that selectively modify liner induced stress
US7442597B2 · kind B2 · utility
12Cited by
4References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 2, 2005 |
| Grant date | Oct 28, 2008 |
| Priority date | — |
| Expiry date | Jan 2, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a semiconductor device. A semiconductor device having one or more regions is provided (102). A strain inducing liner is formed over the semiconductor device (104). A selection mechanism, such as a layer of photoresist or UV reflective coating is applied to the semiconductor device to select a region (106). The selected region is treated with a stress altering treatment that alters a type and/or magnitude of stress produced by the selected region (108).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.