Integrated ball and via package and formation process
US7442641B2 · kind B2 · utility
3Cited by
2References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 5, 2005 |
| Grant date | Oct 28, 2008 |
| Priority date | — |
| Expiry date | Apr 11, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of processing a semiconductor device is provided. The method includes providing a semiconductor device supported by a carrier structure. The carrier structure defines a plurality of vias from a first surface of the carrier structure adjacent the semiconductor device to a second surface of the carrier structure. The method also includes extending a conductor through one of the vias such that a first end of the conductor at least partially extends below the second surface. The method also includes electrically coupling another portion of the conductor to a portion of the semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.