Single stage cyclic analog to digital converter with variable resolution
US7443333B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2007 |
| Grant date | Oct 28, 2008 |
| Priority date | — |
| Expiry date | Apr 15, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/46
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A converter (200) adapted to convert an analog input signal into a digital output signal includes an analog input terminal (205) for receiving the analog input signal, a Redundant Signed Digit (RSD) stage (210) coupled to the analog input terminal, and a digital section (220). The RSD stage is configured to receive the analog input signal at the analog input terminal, produce a first number of bits at a digital output from the analog input signal during a first half of a first clock cycle, provide a residual feedback signal of the analog input signal at the analog input terminal during a second half of the first clock cycle, and produce a second number of bits at the digital output from the residual feedback signal during a first half of a second clock cycle, the second number of bits less than the first number of bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.