Memory erase management system
US7443712B2 · kind B2 · utility
4Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2006 |
| Grant date | Oct 28, 2008 |
| Priority date | — |
| Expiry date | Nov 28, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory erase management system is provided, including providing a resistive change memory cell, coupling a first line to the resistive change memory cell, coupling a line buffer to the first line, providing a charge storage device coupled to the line buffer, and performing a single pulse erase of the resistive change memory cell by discharging a current from the charge storage device through the resistive change memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.