System and method of interleaving transmitted data
US7444556B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 13, 2005 |
| Grant date | Oct 28, 2008 |
| Priority date | — |
| Expiry date | May 24, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0071
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method (500) is provided for operating an interleaver circuit 120 having N shift lines (2201-220N). Each shift line has a line input node, a line output node, and one or more bit storage elements (240). The method includes: storing don't-care bits in each bit storage element (520); isolating the line output nodes from an interleaver output node (520); receiving a stream of data bits at an interleaver input node (530); and sequentially connecting the interleaver input node to respective line input nodes to shift the stream of data bits into the bit storage elements of corresponding shift lines in an interleaved fashion (530). A don't-care bit is shifted out of each of the bit storage elements in corresponding shift lines as each data bit is shifted in. A last don't-care bit is shifted out of respective bit storage elements in the shift lines during N consecutively-received data bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.