Calibration on wafer sweet spots
US7444615B2 · kind B2 · utility
13Cited by
1References
25Claims
0Family size
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Key dates
| Filing date | May 31, 2005 |
| Grant date | Oct 28, 2008 |
| Priority date | — |
| Expiry date | Jul 31, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/68
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method for generating an OPC model is provided which takes into consideration across-wafer variations which occur during the process of manufacturing semiconductor chips. More particularly, a method for generating an OPC model is provided which takes into consideration across-wafer variations which occur during the process of manufacturing semiconductor chips based on the parameters of test patterns measured at the “wafer sweet spots” so as to arrive at an accurate model.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.