Method for error reduction in lithography
US7444616B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 2004 |
| Grant date | Oct 28, 2008 |
| Priority date | — |
| Expiry date | Aug 23, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/70625
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
The present invention relates to a method and a system for predicting and/or measuring and correcting geometrical errors in lithography using masks, such as large-area photomasks or reticles, and exposure stations, such as wafer steppers or projection aligners, printing the pattern of said masks on a workpiece, such as a display panel or a semiconductor wafer. A method to compensate for process variations when printing a pattern on a workpiece, including determining a two-dimensional CD profile in said pattern printed on said workpiece, generating a two-dimensional compensation file to equalize fluctuations in said two-dimensional CD-profile, and patterning a workpiece with said two-dimensional compensation file.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.