Patent · US Active

Chip receptacle, method for fabricating a chip receptacle and chip transport container

US7445119B2 · kind B2 · utility

1Cited by

4References

49Claims

0Family size

Assignee

OSRAM Opto Semiconductors GmbH · DE

Inventors

Mathias Kaempf · Burglengenfeld, DE
Frank Singer · Regenstauf, DE
Jürgen Dachs · Baar-Ebenhausen, DE
Alfred Bachler · Zeitlarn, DE

Key dates

Filing date	Apr 29, 2004
Grant date	Nov 4, 2008
Priority date	—
Expiry date	Dec 11, 2026

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY10S414/135
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Cavities for holding semiconductor chips are etched anisotropically into a semiconductor wafer. An orientation of the wafer in the (100) pulling direction results in geometrically exactly etched sidewalls of the cavities with an angle of 125.3°. What is thereby achieved is that chips can slip into the cavity with a low risk of damage. A transparent cover plate is situated on the cavity plate.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.