Methods and apparatus for RF shielding in vertically-integrated semiconductor devices
US7446017B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2006 |
| Grant date | Nov 4, 2008 |
| Priority date | — |
| Expiry date | Sep 29, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/12044
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A patterned ground shield (PGS) (130) in a vertically-integrated structure includes a patterned conductor (e.g., a metallic layer) provided between a first substrate (110) having a first semiconductor device (1120 formed therein and a second substrate (120) having a second device (122) formed therein. A bonding layer (140) is used to bond the vertically-integrated die and/or wafers. The PGS may be formed on a surface (e.g., the backside) of the second (topmost) substrate, or may be formed over the first semiconductor device—for example, on a dielectric layer formed over the first semiconductor device. The PGS may consist of parallel stripes in various patterns, or may be spiral-shaped, lattice-shaped, or the like.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.