Method of forming vertical FET with nanowire channels and a silicided bottom contact
US7446025B2 · kind B2 · utility
138Cited by
3References
1Claims
0Family size
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Key dates
| Filing date | Apr 30, 2007 |
| Grant date | Nov 4, 2008 |
| Priority date | — |
| Expiry date | May 1, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/938
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A vertical FET structure with nanowire forming the FET channels is disclosed. The nanowires are formed over a conductive silicide layer. The nanowires are gated by a surrounding gate. Top and bottom insulator plugs function as gate spacers and reduce the gate-source and gate-drain capacitance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.