Quasi-vertical LDMOS device having closed cell layout
US7446375B2 · kind B2 · utility
38Cited by
63References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2006 |
| Grant date | Nov 4, 2008 |
| Priority date | — |
| Expiry date | Jul 19, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/519
Abstract
A low voltage power device includes a plurality of quasi-vertical LDMOS device cells. A conductive trench sinker is formed through the epitaxial layer and adjacent a selected one of the source and drain regions in each cell. The trench sinker electrically couples the selected one of the source and drain regions to the substrate for coupling current from the channel to the substrate. The resulting device exhibits a vertical current flow between the metal electrode covering the front surface and the second electrode formed at the back side of the wafer. The device cells are arranged in a closed cell configuration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.