PVT variation detection and compensation circuit
US7446592B2 · kind B2 · utility
9Cited by
9References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2006 |
| Grant date | Nov 4, 2008 |
| Priority date | — |
| Expiry date | Dec 30, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00384
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A compensation circuit and a method for detecting and compensating for process, voltage, and temperature (PVT) variations in an integrated circuit. The integrated circuit includes plural logic modules that include PMOS transistors and NMOS transistors. The compensation circuit includes first and second functional modules, which generate first and second calibration signals. The first and the second calibration signals are used to compensate for the PVT variations in PMOS and NMOS transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.