NBTI-resilient memory cells with NAND gates
US7447054B2 · kind B2 · utility
9Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2006 |
| Grant date | Nov 4, 2008 |
| Priority date | — |
| Expiry date | Jan 2, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/56
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An NBTI-resilient memory cell is made up of a ring of multiple NAND gates. The NAND gates are arranged such that one of the NAND gates has a “0” in its output, while the remaining NAND gates have a “1” in their outputs. PMOS transistors within the memory cell experience less degradation than in inverter-based memory cells. Guard-banding to account for transistor degradation may be mitigated, or the operating frequency of the memory cell may be increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.