Xavier Vera
29Patents
7h-index
22Co-inventors
65Inventor score
Filing activity: Oct 10, 2005 → Jun 13, 2017
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8074110B2 | Enhancing reliability of a many-core processor | Emerging Cross-Sectional Technologies | 31 | Active |
| US8151094B2 | Dynamically estimating lifetime of a semiconductor device | Physics | 18 | Active |
| US8291168B2 | Disabling cache portions during low voltage operations | Emerging Cross-Sectional Technologies | 11 | Active |
| US7447054B2 | NBTI-resilient memory cells with NAND gates | Physics | 9 | Active |
| US8103830B2 | Disabling cache portions during low voltage operations | Emerging Cross-Sectional Technologies | 8 | Active |
| US9071281B2 | Selective provision of error correction for memory | Physics | 8 | Active |
| US7689804B2 | Selectively protecting a register file | Physics | 7 | Active |
| US7600145B2 | Clustered variations-aware architecture | Physics | 6 | Expired |
| US8090996B2 | Detecting soft errors via selective re-execution | Physics | 6 | Active |
| US9112537B2 | Content-aware caches for reliability | Emerging Cross-Sectional Technologies | 6 | Active |
| US7747913B2 | Correcting intermittent errors in data storage structures | Physics | 4 | Active |
| US7558992B2 | Reducing the soft error vulnerability of stored data | Physics | 4 | Active |
| US9286172B2 | Fault-aware mapping for shared last level cache (LLC) | Emerging Cross-Sectional Technologies | 3 | Active |
| US7577015B2 | Memory content inverting to minimize NTBI effects | Physics | 3 | Active |
| US8069376B2 | On-line testing for decode logic | Physics | 3 | Active |
| US9405647B2 | Register error protection through binary translation | Physics | 2 | Active |
| US9170947B2 | Recovering from data errors using implicit redundancy | Emerging Cross-Sectional Technologies | 2 | Active |
| US9075904B2 | Vulnerability estimation for cache memory | Physics | 2 | Active |
| US9678878B2 | Disabling cache portions during low voltage operations | Emerging Cross-Sectional Technologies | 2 | Active |
| US9043659B2 | Banking of reliability metrics | Physics | 2 | Active |
| US8352812B2 | Protecting data storage structures from intermittent errors | Physics | 2 | Active |
| US9176895B2 | Increased error correction for cache memories through adaptive replacement policies | Emerging Cross-Sectional Technologies | 1 | Active |
| US8578137B2 | Reducing aging effect on registers | Physics | 1 | Active |
| US9608922B2 | Traffic control on an on-chip network | Emerging Cross-Sectional Technologies | 1 | Active |
| US8402310B2 | Detecting soft errors via selective re-execution | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.