Memory with retargetable memory cell redundancy
US7447066B2 · kind B2 · utility
34Cited by
72References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2005 |
| Grant date | Nov 4, 2008 |
| Priority date | — |
| Expiry date | Feb 24, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a memory array having redundant columns, a scheme allows defective cells to be individually remapped to redundant cells in a redundant column. Redundant cells in one redundant column replace defective cells in multiple non-redundant columns. Remapping is done as part of initial test and configuration. Specific hardware can be used for the scheme or firmware in the memory controller can implement the scheme.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.