Referencing scheme for trap memory
US7447077B2 · kind B2 · utility
1Cited by
21References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 7, 2006 |
| Grant date | Nov 4, 2008 |
| Priority date | — |
| Expiry date | May 23, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3459
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reference circuit is described for creating a reference signal using a twin MONOS memory cell. A first portion of the twin MONOS memory cell connects to a charged and floating bit line a current source formed in a second portion of the twin MONOS cell that discharges the charged bit line to form a reference signal for a sense amplifier. The sense amplifier compares the reference signal to a signal from a selected memory cell upon which memory operations are being performed comprising read, erase verify and program verify.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.