Modeling asynchronous behavior from primary inputs and latches
US7447620B2 · kind B2 · utility
5Cited by
28References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2006 |
| Grant date | Nov 4, 2008 |
| Priority date | — |
| Expiry date | Aug 12, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Asynchronous behavior of a circuit is emulated by modifying a netlist to insert additional logic at a driving element such as a latch. The additional logic outputs one of (i) a present output from the driving element, (ii) a delayed output from the driving element, or (iii) a random value, which drives downstream logic. The output of the additional logic is selectively responsive to a user-controlled skew enable input. The invention allows for simpler data skew logic transformations which are applicable to both latches and primary inputs, with no dependencies on any clock net.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.