Allocation of branch target cache resources in dependence upon program instructions within an instruction queue
US7447883B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2006 |
| Grant date | Nov 4, 2008 |
| Priority date | — |
| Expiry date | Dec 25, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system includes an instruction fetching circuit 2, an instruction queue 4 and further processing circuits 6. A branch target cache, which maybe a branch target address cache 8, a branch target instruction cache 10 or both, is used to store branch target addresses or blocks of instructions starting at the branch target respectively. A control circuit 12 is responsive to the contents of the instruction queue 4 when a branch instruction is encountered to determine whether or not storage resources within the branch target cache 8, 10 should be allocated to that branch instruction. Storage resources within the branch target cache 8, 10 will be allocated when the number of program instructions within the instruction queue is below a threshold number and/or the estimated execution time of the program instructions is below a threshold time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.