Handling memory errors in response to adding new memory to a system
US7447943B2 · kind B2 · utility
7Cited by
7References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 28, 2003 |
| Grant date | Nov 4, 2008 |
| Priority date | — |
| Expiry date | Nov 6, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a mechanism to detect addition of a memory module. In response to the addition of the memory module, a memory test is run to test the new memory module for a defect. If an uncorrectable error is detected, a routine is activated to process the error. Depending on whether the defect occurred in the new memory module or existing memory module(s), different processing is performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.