Method of fabricating poly silicon layer
US7449377B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2006 |
| Grant date | Nov 11, 2008 |
| Priority date | — |
| Expiry date | Jul 14, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/0227
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a poly silicon layer comprising the following steps is provided. First, a substrate is provided and an amorphous silicon layer is formed on the substrate. A patterned metal layer is formed on the amorphous silicon layer. Next, a pulsed rapid thermal annealing process is performed to form a metal silicide between the patterned metal layer and the amorphous silicon layer, wherein the patterned metal layer and the amorphous silicon layer are adopted for conducting thermal energy to the amorphous silicon layer such that the amorphous silicon layer is converted into a polysilicon layer. Finally, the patterned metal layer is removed. Accordingly, the above processes may prevent the poly silicon layer from metal contamination.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.