Patent · US Active

Master bias current generating circuit with decreased sensitivity to silicon process variation

US7449941B2 · kind B2 · utility

1Cited by

6References

18Claims

0Family size

Assignee

Micron Technology, Inc. · US

Inventors

Ali E. Zadeh · Sierra Madre, US
Ashirwad Bahukhandi · Sunnyvale, US

Key dates

Filing date	Aug 25, 2006
Grant date	Nov 11, 2008
Priority date	—
Expiry date	Dec 21, 2026

Classification

Technology area (CPC G)Physics
CPC primaryG05F3/30
WIPO fieldControl
WIPO sectorInstruments

Abstract

A master bias current generating circuit includes a current source, a first reference leg, and a second reference leg. The first reference leg includes a first transistor having a first size parameter coupled to the current source and a first diode having a second size parameter coupled to the first transistor. The second reference leg includes a second transistor having a third size parameter less than the first size parameter coupled to the current source and a second diode having a fourth size parameter greater than the second size parameter coupled to the second transistor.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.