Phase-change memory device
US7450415B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2006 |
| Grant date | Nov 11, 2008 |
| Priority date | — |
| Expiry date | Dec 19, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A phase-change memory device is provided. The phase-change memory device includes a phase-change memory cell array including a first memory block having a plurality of phase-change memory cells each connected between each of a plurality of bit lines and a first word line, a second memory block having a plurality of phase-change memory cells each connected between each of the plurality of bit lines and a second word line, and first and second pull-down transistors pulling-down each voltage level of the first and the second word lines and sharing a node and a row driver including a first and a second pull-up transistor pulling-up each voltage level of the first and the second word lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.