Methods of operating non-volatile memory cells having an oxide/nitride multilayer insulating structure
US7450423B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2007 |
| Grant date | Nov 11, 2008 |
| Priority date | — |
| Expiry date | Feb 12, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/685
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of operating a memory cell by applying a positive voltage to the gate sufficient to cause hole tunneling from the gate toward the charge storage layer is disclosed. The method is applied to a memory cell including a semiconductor layer having at least two source/drain regions disposed below a surface of the semiconductor layer and separated by a channel region. The memory cell also has a lower insulating layer disposed above the channel region; a charge storage layer disposed above the lower insulating layer; an upper insulating multi-layer structure disposed above the charge storage layer. The upper insulating multi-layer structure comprises a lower dielectric layer and an upper nitride layer disposed above the lower dielectric layer and the memory cell has a gate disposed above the upper insulating multi-layer structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.